Lesson 051: Pulse-level vs gate-level glossary
Focus
Assume every diagram must map to topology and basis gates—not textbook abstractions alone. Token Pulse-level vs gate-level glossary:51 keeps neighbouring lessons differentiable.
Key ideas
- Thread: Pulse-level vs gate-level glossary · drill v1 · spin
497228. - Habit: pair each job with shot budget, mitigation profile, and a calibration fingerprint you could paste.
- Guardrail: write one line about where classical cost dominated the timeline.
Deep dive notebook
Synthetic drill artefacts
Circuit sketch (logical → ISA)
LOGICAL_LINES: q2, q1, aux2
TOPOLOGY_TAG: RIG-51
NATIVE_ISA: {CX, Rz, RX}
SWAP_STRATEGY: bridge@0.43
NOTES: lesson 51 micro 0
DEPTH_WATCH: abort if brute-force swaps > D_MAX without SME sign-off memo.
Practice
Practice List five failure signatures unique to your organiser’s QPUs or simulators. — 51 Bump literals mindset by 22.